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HOME / Product / Mobile TV / TRITON-II
TRITON-II
TRITON-II is a high-performance multimedia processor, which is optimized for use in feature Mobile TV phone applications. This ARM-based processor delivers unprecedented performance, and integrates all kinds of Mobile TV standard features such as , T-DMB, DVB-H, ISDB-T, S-DMB , and more. TRITON-II also has cost effective, ultra low size and 65 nm process enables low power consumption
 


 Advantages of TRITON-II

- TRITON-II is a dedicated mobile TV chip that supports video decoding with H.264 baseline level 1.3, and
  programmable 
  audio functions according to application with BSAC/AAC/AAC+ V1/AAC+ V2/MP3/WMA.
- H.264 for video decoding for global mobile TV service is implemented in a hardware level, providing maximum 
  performance with minimum power consumption. TRITON-II is designed to process CIF-class H.264 standard video
  at 60 frames per second. Users can play the stored program at multiple rate, or when using the time machine function,
  catch up the scene in play at multiple access rate or a slightly faster rate.
- With the built-in ARM CPU, TRITON-II enables various levels of processing in the S/W level, and supports OS porting
  for system operation and various APIs and application programs. TRITON-II also has the peripherals for interface with
  various types of CPU and other peripherals.
- TRITON-II supports SPI Slave and HOST I/F Boot for combined use with HOST CPU, and various booting modes such
  as Serial Flash and NAND Flash.
- The LCD controller supports free size display of SVGA grade, and the Image Enhancement function implements
  the high-resolution LCD display. With the image filtering, OSD (On Screen Display) and video format
  conversion function, the LCD provides self post processing without any additional function.
  The LCD also has the external TV encoder interface, supporting TV output with optional external TV_ENC.
- The power control scheme supports long mobile-TV playing on the handheld device.
- TRITON-II supports various PKG options, including the 6x6 PKG size for easy PCB design for mobile phone solution
  and the PKG for vehicles.



 
Key features

Video CODEC
   - hardwired H.264 Decoder
     * decoding performance : 30fps@CIF
     * High performance with low frequency and power consumption
     * In-loop de-blocking filter for H.264 Decoder

CPU architecture
   - ARM926EJ based architecture
   - 16KB D-cache / 16KB I-Cache with MMU for supporting 
   - Linux, Nucleus, and more.
   - Debug port with an embedded trace module
   - AMBA2.0, AHB/APB architecture
   - Includes Java acceleration

Memory subsystem
   - Embedded SDRAM with MCP
   - SDRAM interface
      * 32bit BUS Width
      * Support Self-refresh/power-down mode
   - Serial Flash interface

Electrical Characteristics
   - Operating condition
       Supply voltage for logic core :
         1.2V +/-10
       External I/O interface :
         1.8¡¾10%/2.8¡¾10%/3.3¡¾10% 
   - Package
       TRITON-IIS5 : 121 FBGA with 64Mbit SDRAM ( 6mm x6mm, 0.5 ball pitch)
       TRITON-IIS1 : 169  FBGA with 128Mbit SDRAM ( 7mmx7mm, 0.5 ball pitch)
       TRITON-II : 196 FBGA ( 12mmx12mm, 0.8 ball pitch)